1. Field of the Invention
The present invention relates to a circuit arrangement for clock pulse recovery at the receiving end of digital clock-controlled data systems.
2. Description of the Prior Art
In various instances of digital data transmission, e.g. pulse code modulation (PCM), delta modulation, diphase codes, etc., it is necessary to generate a timing pulse which is bit-synchronized with the digital data, i.e. synchronous in frequency and phase, for receiving.